Bangalore
5+ years design engineering (middle tier/end design)
Timing for constraints
RTL PPA Analysis
Should be familiar with Chip level synthesis, RTL, Timing Constraints
Education: Bachelors/Masters, Electric Engineering/Computer Science or relevant
Experience | 7 - 13 Years |
Salary | 9 Lac To 35 Lac P.A. |
Industry | IT Software - Application Programming / Maintenance |
Qualification | Other Bachelor Degree |
Key Skills | ASIC RTL Coding VLSI Design ASIC Engineer Electric Engineer Walk in |
(253)Manufacturing / Production / Q...
(136)Sales & Marketing / Business D...
(112)IT Software - Application Prog...
(102)Health Care / Pharmaceuticals ...
(51)Education / Teaching / Trainin...
(45)Engineering / Engineering Desi...
(40)ITES / BPO / KPO / LPO / Custo...
(38)Hotel / Restaurants / Travel /...
(34)Financial Services / Banking, ...
(29)HR / Recruitment / Administrat...
(25)Accounting / Auditing / Taxati...
(21)Real Estate / Construction
(16)IT Software - Ecommerce / Inte...
(14)IT Hardware / Technical Suppor...
(13)IT Software - Mobile Technolog...
(13)Cargo / Freight / Transportati...
(12)Analytic and Business Intellig...
(11)Content Writing
(9)Front Office / Reception / Com...
(9)IT Software - QA / Testing / D...
(9)Marketing / Advertising / PR /...
(9)IT Software - ERP / CRM / EDP ...
(9)IT Software - Client Server
(9)Legal / Law Services / Judicia...
(8)Supply Chain / Purchase / Proc...
(8)Media / Entertainment / TV / ...
(8)Corporate Planning & Strategy ...
(7)IT Software - System Programmi...
(7)Public Relation (PR) / Advert...
(4)IT Software - DataBase / Dataw...
(4)Architecture / Interior Design
(3)Beauty / Fitness / Spa Service...
(3)Self Employed / Entrepreneur /...
(3)Oil / Gas / Petroleum / Solar ...
(2)IT Software - Network Administ...
(2)Fashion Designing & Merchandis...
(1)Export / Import / Merchandisin...
(1)IT Hardware – Security / Ope...
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