Hi! Simply click below and type your query.
Our experts will reply you very soon.
BS (or equivalent experience) / MS with 2+ years of experience in design verification.
Exposure to design and verification tools (Verilog/SV or equivalent, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
C/C++ programming/scripting language experience desirable.
|Experience||8 - 14 Years|
|Salary||10 Lac To 40 Lac P.A.|
|Industry||Engineering / Engineering Design / R&D / Quality|
|Qualification||Other Bachelor Degree|
|Key Skills||Chip Design Chip Design Verification Engineer C C++ Verilog|
|Address||Talent Zone Consultant, Sampige Road|
(16)Content WritingView More