Bangalore
BS (or equivalent experience) / MS with 2+ years of experience in design verification.
Exposure to design and verification tools (Verilog/SV or equivalent, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
C/C++ programming/scripting language experience desirable.
Experience | 8 - 14 Years |
Salary | 10 Lac To 40 Lac P.A. |
Industry | Engineering / Engineering Design / R&D / Quality |
Qualification | Other Bachelor Degree |
Key Skills | Chip Design Chip Design Verification Engineer C C++ Verilog Walk in |
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