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1. Minimum 5 years of experience in Verification Engineer.
2. Good communication, good digital knowledge and problem-solving skills .
3. Good scripting knowledge using perl / python.
4.Strong SV & UVM skills .
5. Good knowledge in any of the protocols like Ethernet/PCIE/USB/DDR/AXI/SATA/MIPI.
6. Experienced in developing test bench components, writing tests and coverage tuning.
7. Digital Design and Verification Verilog/System-Verilog Common Skills.
Location :Bangalore, Chennai, pune
|Experience||5 - 7 Years|
|Industry||Manufacturing / Production / Quality|
|Qualification||B.C.A, B.Sc, B.Tech/B.E, M.C.A, M.Sc, M.Tech|
|Key Skills||System Verilog Digital Design SV UVM Verification Engineer|
|Address||Talent Zone Consultant, Sampige Road|
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